Question: Implement the data memory shown below in VHDL/verilog. Write a value into the memory location and read a value from the memory location. Write always
Implement the data memory shown below in VHDL/verilog. Write a value into the memory
location and read a value from the memory location. Write always happens on the rising edge of the clock and when WE (write enable) is set high. The data and address lines are 32 bits
wide.
Please have a screenshot of the waves.
CLK WE ARD 32 32 WD 32
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