In this exercise, we examine how pipelining affects the clock cycle time of the processor. individual stages of the datapath have the following latencies: 4. Assume the MEM 300 ps WB 200 ps IF ID 350 ps EX 150 ps 250 ps What is the clock cycle time in a pipelined and non-pipelined processor? Pipelined: 350 ps Non-pipelined: 1250 ps What is the total latency of an lw instruction in pipelined and non-pipelined processor? Pipelined: Five clockcycle @ 350 ps 1750 ps Non-pipelined: 250+350+ 150+300+ 200 1250 ps...-. one clock cycle@ 1250- If we can sp the original stage, which stage would you split and wh ID, the new clock cycle time will be 300 ps. a. b. 1250 ps lit one stage of the pipelined datapath into two new stages, each with half the latency of at is the new clock cycle time of the processor? c