Question: in VHDL code. Write VHDL code to implement the following truth table. The signals a2, al, and a0 are inputs. The signals b1 and b0

in VHDL code.

Write VHDL code to implement the following truth table. The signals a2, al, and a0 are inputs. The signals b1 and b0 are outputs. a2 a1 a0 b1 b0 0 0 0 0 0 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 1 0 1 0 0 1 1 1 0 0 1 1 1 0 1

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