library ieee;

use ieee.std_logic_1164.all ;

entity function1 is

port ( A : in std_ulogic;

B : in std_ulogic ;

C : in std_ulogic ;

Y :out std_ulogic);

end function1;

architecture decription of function1 is begin

P1: process

variable temp1: bit ;

variable temp2: bit ;

variable temp3: bit ;

begin temp1 <= not A after 1 ns;

temp2 <= A AND C after 1ns;

temp3 <= temp1 AND B after 1ns;

Y <= temp2 OR temp3 after 1ns;

end description;

Problem 4: Copy the SOP circuit above to a new VHDL file, and increase the delay of the output OR gate. Simulate the circuit and answer the questions below.

How did adding delay to the output gate change the output transition?

Does adding delay to the output gate change the circuits glitch behavior in any way?