Sample VHDL Code

library ieee;

use ieee.std_logic_1164.all;

--------------------------------------

entity OR is

port( a: in std_logic;

b: in std_logic;

X: out std_logic

);

end OR;

---------------------------------------

architecture OR_arch of OR is

begin

process(a, b)

begin

-- compare to truth table

if ((a='0') and (b='0')) then

X <= '0';

else

X <= '1';

end if;

end process;

end OR_arch;

architecture OR_beh of OR is

begin

X <= a or b;

end OR_beh;

Questions:

1. What is VHDL ? What are capabilities of VHDL ?

2. What is the use of entity and Architecture block in a VHDL code?

3. What is the difference between Verilog and VHDL?

4. Write a VHDL code for full adder.