mainly question a) and. b) please.

Regwrite Read Instruction address (31-0] 1 [25. 21) Mem Write MemToReg 1 [20 - 16] ALU Zero Instruction memory Read Read register 1 data 1 Read register 2 Read data 2 Write register Registers Write data Result M 200 ps Read Read address data Write address Data Write memory data 200 ps Mem Read 200 ps 1 [15.11) ALUOp Ops 100 ps Ons Reg Dst 1 [15-0) Tops ALUSC Sign extend Ops (i) List the steps and calculate the total time needed to complete the MIPS bitwise AND instruction (i.e. and $s1, $s2, $s3). [3] (ii) Use the table below to give the control line signals for the MIPS bitwise AND instruction. [3] RegDst Reg Write ALUSrc ALUOp MemRead Mem Write MemToReg c) Discuss the major issue with the single cycle datapath model. State the technique as well as the additional datapath elements that must be added to improve on this model. List the problems that come with the improved model. [5]