Question: / / max 2 . sv module max 2 ( input logic [ 7 : 0 ] A , input logic [ 7 : 0

// max2.sv
module max2
(
input logic [7:0] A,
input logic [7:0] B,
output logic [7:0] Z
);
assign Z = A ; // FIXME
endmodule //max2

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