Question: module matrixops ( input clk , input rst , input enter, input [ 1 : 0 ] X , input [ 1 : 0 ]

module matrixops (
input clk,
input rst,
input enter,
input [1:0] X,
input [1:0] Y,
output reg Z
);
//4x4 matrix of single-bit cells
reg matrix[3:0][3:0];
// State Encoding:
//0: S_WAIT_START
//1: S_GET_INPUTS
//2: S_DONE
reg [1:0] state;
reg [2:0] input_count; // count up to 5 sets
// Intermediate register for one-cycle delay for Z
reg Z_buffer;
always @(posedge clk or posedge rst) begin
if (rst) begin
// On reset, initialize everything
Z <=0;
Z_buffer <=0;
state <=0; // S_WAIT_START
input_count <=0;
// Manually initialize each cell of the matrix to 0 without a for loop
matrix[0][0]<=0;
matrix[0][1]<=0;
matrix[0][2]<=0;
matrix[0][3]<=0;
matrix[1][0]<=0;
matrix[1][1]<=0;
matrix[1][2]<=0;
matrix[1][3]<=0;
matrix[2][0]<=0;
matrix[2][1]<=0;
matrix[2][2]<=0;
matrix[2][3]<=0;
matrix[3][0]<=0;
matrix[3][1]<=0;
matrix[3][2]<=0;
matrix[3][3]<=0;
end else begin
case (state)
0: begin
// S_WAIT_START
if (enter ==1) begin
state <=1; // S_GET_INPUTS
input_count <=0;
Z_buffer <=0;
end
end
1: begin
// S_GET_INPUTS
if (enter ==1) begin
matrix[Y][X]<=1'b1;
input_count <= input_count +1;
if (input_count ==4) begin
// After 5 inputs, move to DONE
state <=2;
end
end
end
2: begin
// S_DONE
if (enter ==1) begin
Z_buffer <= matrix[Y][X];
end
end
endcase
// Assign Z from Z_buffer at the end of the cycle (one-cycle delay)
Z <= Z_buffer;
end
end
endmodule
I need to draw an ASM chart for this verilog code

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