N. Write a Verilog code that describes the following figure. The figure represents the register file (32x32) with its inputs and outputs as shown. Assume that the register outputs are updated asynchronously but writing to the register is updated with an available address at wn (not-0), we signal-1, synchronously with every positive edge clock cycle and synchronously with the (rst signal-1). You have to reset all the register values when there is a reset signal. (4 points) 5-bit register number of read port A 5-bit register number of read port B 5-bit register number of write port 32-bit data of write port regtile 32-bitdata of read port A 32-bit data of read port B -?? ma40] qtal opto enable !' wu cirn write dock dlear