N-bit posieve edge triggered shift regis lied finish the lesbench code without changing, of the code pven Behavlour Modeling of N-bit to H-Bit Shift RegisteriMN) Library 1eee: ieee.std Logic 1164.all; tity NShiTER port (Clk,CIr.Ld.Sh, D1: in std logic: D:in std Logic vector: Q: out std logic wector): NShiftR hitecture Behave of NShiftR is ift: process (Cr, Ck) subtype Ds is naturat range D'Length-1 downto subtype Os is satural range Q'Length-1 dounto variable Tm: std Logic vector(0s) Clr" "I' then -(others elsif Ck'Event and Clk 3 then if Ld '1" then Tm (others '1 else case Di is when when when '0' '1 others "> Tm :- '0' & Tm(Tn.Left downto 1); ", Tn:" '. & Tm(Tm,Left downto 1); 0 Tm :- '0' & Tm(Tn.Left downto 1); ", Tn:" '. & Tm(Tm,Left downto 1); 0