Question: No . 1 . Verilog half adder. Write Verilog Program for Half Adder. You are provided with code for Structural, Data flow and Behavioral representations

No.1. Verilog half adder.
Write Verilog Program for Half Adder. You are provided with code for Structural, Data flow and Behavioral representations of code. You can see only structural representation is active. Other two are commented. Please execute all three representations. Provide screenshots for your execution and output. Please fix errors if you find any.
```
module half_adder(
input a,// Input 'a'
input b,// Input 'b'
output s,// Output 's'(Sum)
output c // Output 'c'(Carry)
);
```
//assign s = a ^ b;// Dataflow expression for sum
//assign c = a & b; // Dataflow expression for carry
xor gate_xor (s, a, b); // XOR gate for sum [ structural representation]
and gate_and (c, a, b); // AND gate for carry [structural represenation]
// Combinational logic equations for sum and carry [Behaviorial representation]
//always @(*) begin
//\(\mathrm{s}=\mathrm{a}^{\wedge}\mathrm{b}\); //XOR operation for sum
//\( c=a \& b ; \)// AND operation for carry
/Iend
endmodule
module half1_adder;
// Declare registers
reg d; // Register 'd' for input '\( a \)' reg e; // Register 'e' for input 'b'
//Declare wires
wire f; // Wire 'f' for output 's'(Sum)
wire g; // Wire 'g' for output '\( c \)'(Carry)
// Instantiate half_adder module
half_adder half2_adder (.a(d),.b(e),.s(f), c(g));
//Initial block for simulation
initial begin
// Test case 1
\$display("test case 1");
\(\mathrm{d}=1\)'b1; // Assign input 'a' as 1
\$display("a=\%b", d); // Display value of input '\( a \)'
\( e=1\)'b1;// Assign input 'b' as 1
\$display("b=\%b", e); // Display value of input ' b '
\#10; // Wait for 10 time units
\$display("s=\%b", f); // Display value of output '\( s \)'(Sum)
\$display("c=\%b", g); // Display value of output ' C '(Carry)
// Test case 2
\$display("test case 2");
\( d=1\)'b0; // Assign input '\( a \)' as 0
\$display("a=\%b", d); // Display value of input 'a'
\( e=1\)'b1; // Assign input 'b' as 1
\$display("b=\%b", e); // Display value of input 'b'
\#10; // Wait for 10 time units
\$display("s=\%b", f); // Display value of output 's'(Sum)
\$display("\(\mathrm{c}=\%\mathrm{~b}^{\prime \prime},\mathrm{g}\)); // Display value of output ' c '(Carry)
// Test case 3
\$display("test case 3"); \( d=1\)'b1; // Assign input 'a' as 1
\$display("a=\%b", d); // Display value of input '\( a \)'
\( e=1\)'b0; // Assign input 'b' as 0
\$display("b=\%b", e); // Display value of input 'b'
\#10: // Wait for 10 time units
\$display("s=\%b", f); // Display value of output 's'(Sum)
\$display("c=\%b", g); // Display value of output 'c'(Carry)
// Test case 4
\$display("test case 4");
\( d=1' b 0 ; //\) Assign input '\( a \)' as 0
\$display("a=\%b", d); // Display value of input 'a'
\( e=1\)'b0; // Assign input 'b' as 0
\$display("b=\%b", e); // Display value of input 'b'
\#10; // Wait for 10 time units
\$display("s=\%b", f); // Display value of output 's'(Sum)
\$display("c=\%b", g); // Display value of output 'c'(Carry)
end
endmodule
No . 1 . Verilog half adder. Write Verilog

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