Objective:

To implement a Verilog gate level model for $32-$bit and $64-$bit Ripple Carry Adders.

Outcome: $$

Gate level implementation for the following components.

TWOSCOMP$64$

TWOSCOMP$32$

Instruction: $$

Continue with your Modelsim Project$03$ as in Lab Assignment $02$

Complete gate level description of following components.

RC$\_$ADD$\_$SUB$\_64$ in rc$\_$add$\_$sub$\_32.$v file

Try to use generate block in a loop this time.

TWOSCOMP$32$ in logic.v file

TWOSCOMP$64$ in logic.v file

Compile entire Project$03$ and simulate following modules in ModelSim simulator.

TWOSCOMP$32\_$TB

TWOSCOMP$64\_$TB

Observe corresponding outcomes on waveform windows and fix any issue.

Each testbench will generate corresponding output file.

OUTPUT$/$twoscomp$32\_$tb$.$out

OUTPUT$/$twoscomp$64\_$tb$.$out

This should match with corresponding golden output file in CS$147-$Project$03/$GOLDEN$/$ directory.

twoscomp$32\_$tb$.$out.golden

twoscomp$64\_$tb$.$out.golden

Add more testing in these testbenches to make sure outcome is correct.

$//$ Name: rc$\_$add$\_$sub$\_32.$v

$//$ Module: RC$\_$ADD$\_$SUB$\_32$

$//$

$//$ Output: Y : Output $32-$bit

$//$ CO : Carry Out

$//$ Input: A : $32-$bit input

$//$ B : $32-$bit input

$//$ SnA : if SnA$=0$ it is add, subtraction otherwise

$//$

$//$ Notes: $32-$bit adder $/$ subtractor implementaiton.

$//$

"include $"$prj$\_$definition.v$"$

module RC$\_$ADD$\_$SUB$\_64($Y$,$ CO$,$ A$,$ B$,$ SnA$)$;

$//$ output list

output $[63$:$0]$ Y:

output CO:

$//$ input list

input $[63$:$0]$ A:

input $[63$:$0]$ B;

input SnA:

$//$ TBD

$\backslash$

endmodule

module RC$\_$ADD$\_$SUB$\_32($Y$,$ CO$,$ A$,$ B$,$ SnA$)$:

$//$ output list

output $["$DATA$\_$INDEX$\_$LIMIT:$0]$ Y:

output CO:

$//$ input list

input $[`$DATA$\_$INDEX$\_$LIMIT:$0]$ A;

input $[`$DATA$\_$INDEX$\_$LIMIT:$0]$ B;

input SnA;

$//$ TBD

endmodule

$//$ Name: logic.v

$//$ Module:

$//$ Input:

$//$ Output:

$//$

$//$ Notes: Common definitions

$//$

$//$ Name: logic.v

$//$ Module:

$//$ Input:

$//$ Output:

$//$

$//$ Notes: Common definitions

$//64-$bit two's complement

module TWOSCOMP$64($Y$,$A$)$;

$//$output list

output $[63$:$0]$ Y;

$//$input list

input $[63$:$0]$ A;

$//$ TBD

endmodule

$//32-$bit two's complement

module TWOSCOMP$32($Y$,$A$)$;

$//$output list

output $[31$:$0]$ Y;

$//$input list

input $[31$:$0]$ A;

$//$ TBD

endmodule

$//32-$bit registere $+$ve edge, Reset on RESET$=0$

module REG$32($Q$,$ D$,$ LOAD, CLK$,$ RESET$)$;

output $[31$:$0]$ Q;

input CLK$,$ LOAD;

input $[31$:$0]$ D;

input RESET;

$//$ TBD

endmodule

$//1$ bit re