Objective

To implement a Verilog gate level model for ripple carry adder subtractor.

Outcome

Gate level implementation for the following components.

FULL$\_$ADDER

HALF$\_$ADDER

RC$\_$ADD$\_$SUB$\_32$

Instruction

Continue with your Modelsim Project$03$ as in Lab Assignment $01$

Complete gate level description of following components

HALF$\_$ADDER module in half$\_$adder.v

FULL$\_$ADDER module in full$\_$adder.v

RC$\_$ADD$\_$SUB$\_32$ module in rc$\_$add$\_$sub$\_32.$v

Compile entire Project$03$ and simulate following testbenches in ModelSim simulator.

HALF$\_$ADDER$\_$TB

FULL$\_$ADDER$\_$TB

RC$\_$ADD$\_$SUB$\_32\_$TB

Observe result on waveform windows and fix any issue.

This will also generate following output files.

OUTPUT$/$half$\_$adder.out

OUTPUT$/$full$\_$adder.out

OUTPUT$/$rc$\_$add$\_$sub$\_32.$out

This should match with given golden file in CS$147-$Project$03/$GOLDEN$/$

half$\_$adder.out.golden

full$\_$adder.out.golden

rc$\_$add$\_$sub$\_32.$out.golden

Add more testing in testbenches to make sure outcome is correct.

$//$ Name: full$\_$adder.v

$//$ Module: FULL$\_$ADDER

$//$

$//$ Output: S : Sum

$//$ CO : Carry Out

$//$

$//$ Input: A : Bit $1$

$//$ B : Bit $2$

$//$ CI : Carry In

$//$

$//$ Notes: $1-$bit full adder implementaiton.

$`$include $"$prj$\_$definition.v$"$

module FULL$\_$ADDER$($S$,$CO$,$A$,$B$,$ CI$)$;

output S$,$CO;

input A$,$B$,$ CI;

$//$TBD

Endmodule;

$//$ Name: half$\_$adder.v

$//$ Module: HALF$\_$ADDER

$//$

$//$ Output: Y : Sum

$//$ C : Carry

$//$

$//$ Input: A : Bit $1$

$//$ B : Bit $2$

$//$

$//$ Notes: $1-$bit half adder implementaiton.

$//$

include $"$prj$\_$definition.v$"$

module HALF$\_$ADDER$($Y$,$ C$,$A$,$B$)$;

output Y$,$C;

input A$,$B;

$//$ TBD

Endmodule;

$//$ Name: rc$\_$add$\_$sub$\_32.$v

Module: RC$\_$ADD$\_$SUB$\_32$

$//$ Output: Y : Output $32-$bit

$//$ CO : Carry Out

$//$

$//$

$//$ Input: A : $32-$bit input

$//$ B : $32-$bit input

$//$ SnA : if SnA$=0$ it is add, subtraction otherwise

$//$

$//$ Notes: $32-$bit adder $/$ subtractor implementaiton.

$//`$include $"$prj$\_$definition.v$"$

module RC$\_$ADD$\_$SUB$\_64($Y$,$ CO$,$ A$,$ B$,$ SnA$)$;

$//$ output list

output $[63$:$0]$ Y;

output CO;

$//$ input list

input $[63$:$0]$ A;

input $[63$:$0]$ B;

input SnA;

$//$ TBD

endmodule

module RC$\_$ADD$\_$SUB$\_32($Y$,$ CO$,$ A$,$ B$,$ SnA$)$;

$//$ output list

output $[`$DATA$\_$INDEX$\_$LIMIT:$0]$ Y;

output CO;

$//$ input list

input $[`$DATA$\_$INDEX$\_$LIMIT:$0]$ A;

input $[`$DATA$\_$INDEX$\_$LIMIT:$0]$ B;

input SnA;

$//$ TBD

endmodule