Part $2$

Assume the code snippet is executed on a five$-$stage pipelined Datapath like the MIPS. Branch prediction occurs in decode stage.

$1.$ LW $\backslash$$t$0,\backslash (0(\backslash$$ s $0)\backslash )$; load a$[0]$

$2.$ ADDI $\backslash$$s$1,$ zero, $2$ ; $\backslash$$s$1=5$

$3.$ ADDI $\backslash$$s$0,\backslash$$s$0,4$; increment memory address

$4.$ LOOP: ADDI $\backslash$$t$1,\backslash$$t$0,0$ ; a$[$i$]=$ a$[$i$-1]$

$5.$ BEQ $\backslash$$t$2,\backslash$$s$3,$ JMARK ; Branch b$1$ ; if $\backslash$$t$2==2$ goto JMARK

$6.$ ADDI $\backslash$$t$1,\backslash$$t$1,1$ ; a$[$i$]=$a$[$i$]+1$

$7.$ JMARK: SW $\backslash$$t$1,\backslash (0(\backslash$$ $\backslash$mathrm$\{$~s$\}0)\backslash )$; store a$[$i$]$

$8.$ ADDI $\backslash$$t$2,\backslash$$t$2,1$ ; increment loop counter

$9.$ ADDI $\backslash$$s$0,\backslash$$s$0,4$ ; increment memory address

$10.$ ADDI $\backslash$$t$0,\backslash$$t$1,0$ ; a$[$i$-1]=$ a$[$i$]$

$11.$ BNEQ $\backslash$$t$1,\backslash$$s$1,$ Loop ; Branch b$2$ ; if $\backslash$$t$1!=\backslash$$s$1$ goto Loop

a$)$ If there is no forwarding or hazard detection, insert NOPs to ensure correct execution.

b$)$ If the processor has forwarding, but we forgot to implement the hazard detection unit, what happens when the original code executes?

c$)$ Assuming there is no forwarding, fill the table below. $($add as many rows as needed$)$

d$)$ Assuming there is forwarding, fill the table below. $($add as many rows as needed$)$

e$)$ Determine the latency of the branching instruction.

Hint: You have to detect and resolve the dependencies, assume Branch predictor is always right $($no control hazards$).$