Question: Part 2: Thought Questions 1 . Explain why the RegWrite control signal is asserted (=1) only when we have R-type or lw instructions, and it

Part 2: Thought Questions 1. Explain why the RegWrite control signal is asserted (=1) only when we have R-type or lw instructions, and it must be de-asserted (=0) for other instructions?

2. Suppose a new instruction will be added to an existing MIPS ISA is given as below: Instruction: SWI Rd, Rt(Rs) Interpretation: Mem[Reg[Rt]+Reg[Rs]]= Reg[Rd]

A. Which existing blocks in MIPS datapath will be accessed for this instruction? Explain. B. Which control signals (and values) do we need from the control unit during the execution of this instruction? Explain.

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