Assume that the logic blocks needed to implement a processors datapath have the following latencies:

I-Mem	Add	Mux	ALU	Regs	D-Mem	Sign-Extend	Shift-Left-2
200ps	70ps	20ps	90ps	90ps	250ps	15ps	10ps

a, if the only thing we need to do in a processor is fetch consecutive instructions , what would the cycle time be?

b, Consider a datapath similar to the one in Figure 4.11, but for a processor that only has one type of instruction: unconditional PC-relative branch. What would be the cycle time for this datapath?

c, Repeat part b), but this time we need to support only conditional PC-Relative branches.

d, Which kind of instructions require datapath element Shift-Left-2?

e, Assume that we only support beq and add instructions, discuss how changes in the given latency of shift-Left-2 affect the cycle time of the processor. Assume that the latencies of other resources do not change.