Which resources (blocks) produce outputs, but their outputs are not used for this instruction? Which resources produce no outputs for this instruction?

Different instructions utilize different hardware blocks in the basic single-cycle implementation. The next three problems in this exercise refer to the following instruction:

a. b. Instruction AND Rd, Rs, Rt SW Rt, Offs (Rs) Interpretation Reg[Rd]=Reg[Rs] AND Reg[Rt] Mem[Reg[Rs]+Offs]=Reg[Rt]