Please convert to Python. Thank You.

library IEEE; use IEEE . STD LOGIC 1164. ALL; use IEEE.STD LOGIC UNSIGNED. ALL; use IEEE . STD LOGIC ARITH. ALL; entity normal is port (Clk : in atd logic; data in : in integer; data out : out integer; a,b,c : in integer ) ; end normal; architecture Behavioral of normal is signal data, result : integer := 0; begin data clk, data in => data in, data out => data_out, a => b =>b, C C a