Question: please help me find out the error in the verilog code `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 14:28:08
please help me find out the error in the verilog code
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:28:08 09/20/2017
// Design Name:
// Module Name: dist_module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module dist_module(
input clk,
input echo,
input reset,
output reg trig,
output distance
);
reg [25:0] dist_counter=0;
reg [25:0] counter=0;
reg distance1;
always @ ( posedge clk)
begin
if(reset)
begin
counter<=0;
distance1<=0;
end
else
begin
counter<=counter+1;
if(counter<=500) // to initialize the sensor wait for 10 sec
begin
trig<=1;
end
if(echo)
begin
dist_counter<=dist_counter+1;
trig<=0;
end
if(counter<=1900000) // max time of sensing for ultrasonic is 38ms
begin
trig<=0;
end
if(counter<=5000000) // wait for 1 sec to begin again
begin
counter <= 0;
distance1 <= 0;
end
end
end
assign distance = distance1;
assign distance =(dist_counter*170);
endmodule
it is giving error
Related source file is "dist_module22.v". WARNING:Xst:643 - "dist_module22.v" line 70: The result of a 26x8-bit multiplication is partially used. Only the 1 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior. Found 1-bit register for signal
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