Problem 4: Multiprocessor Cache Coherence (13 points) Assume a 2 processor shared memory system with private cache in each processor, and a snooping bus cache coherence protocol using write invalidate. Now consider the following sequence of operations from two processors, labeled P1 and P2, to shared data.(Assume initial values in memory A-20 and 8-10 and assume they map to different cache blocks.) P1: Read A P2: Read A P1: Write A-40 P2: Read A P2: Read Bs P2: Write B-50 P1: Read A Describe the sequence of events generated (on bus and processor) the actions taken, and the state of the cache and memory during the execution of the above code. (You should explain events at each step/cycle; you can explain it using a figure/table similar to the case study from the text, or write out sentences that describe the behavior.)