Question: Problem 5 (12 points): Assume that main memory accesses take 20ns and that 30% of all instructions access data memory. The following table shows data

Problem 5 (12 points):\ Assume that main memory accesses take

20ns

and that

30%

of all instructions access data memory. The following table shows data for L1 caches attached to each of two processors, P1 and P2.\ \\\\table[[,L1 size,L1 miss rate,L1 hit time],[P1,

2KB

5%

0.2ns

$Problem 5 (12 points):\ Assume that main memory accesses take 20ns$

Problem 5 (12 points): Assume that main memory accesses take 20ns and that 30% of all instructions access data memory. The following table shows data for L1 caches attached to each of two processors, P1 and P2 a) Assuming that the L1 hit time determines the cycle times for P1 and P2, what are their respective clock rates (4 points)? b) What is the Average Memory Access Time for P1 and P2 (in cycles) (8 points)

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