Q 1(a) Consider the Data Flow Graph (DFG) below. Assuming that the multipliers and adders take 1 time unit, identify all the loops in the DFG and compute the critical loop bound [12 Marks] 3 2 4 11 10 Q 1(b) For the DFG in Q1 (a), calculate the critical path delay [5 Marks] Q 1(c) Perform a retiming of the DFG, in Q1 (a). Draw the retimed DFG and calculate the new critical path delay. Explain the retiming methods used and describe/draw each step. [10 Marks] Q 1(d) Real time digital signal processing (RT DSP) may be divided into three categories based on their performance; name and explain each of them (furnish your explanation with examples) [6 Marks]