Q. 27

///////////////////////////////DESIGN///////////////////////////////

module apb( input pclk, input presetn, input pwrite, input psel, input penable, input [31:0] paddr, input [31:0] pwdata, output reg [31:0] prdata, output reg pready ); reg [31:0] memory [1023:0]; reg [1:0]state; parameter IDLE = 2'b00, SETUP = 2'b01, ACCESS = 2'b10; always @(posedge pclk or negedge presetn) begin if( presetn == 1'b0) begin state <= IDLE; end else begin case(state) IDLE : begin if(psel == 1'b1 && penable == 1'b0 ) begin state <= SETUP; end else if(psel == 1'b1 && penable == 1'b1) begin state <= SETUP; end else begin state <= IDLE; end end SETUP : begin if( psel == 1'b1 && penable == 1'b1) begin state <= ACCESS; end else if(psel == 1'b1 && penable == 1'b0) begin state <= SETUP; end else begin state <= IDLE; end end ACCESS : begin if( psel == 1'b1 && penable == 1'b1) begin state <= ACCESS; end else if( psel == 1'b1 && penable == 1'b0) begin state <= SETUP; end else begin state <= IDLE; end end endcase end end always@(psel,penable,pready,state) begin if(pwrite == 1'b1 && state == ACCESS && psel == 1'b1 && pready == 1'b1) memory[paddr] <= pwdata; else if(pwrite == 1'b0 && state == ACCESS && psel == 1'b1 && pready == 1'b1) prdata <= memory[paddr]; end

always@(penable) begin if(penable == 1'b1) begin pready <= 1'b1; end else begin pready <= 1'b0; end end endmodule

///////////////////////////////////TESTBENCH////////////////////////////////

module apb_test; reg pclk; reg presetn; reg [31:0] paddr; reg [31:0] pwdata; reg pwrite; reg psel; reg penable; wire [31:0]prdata; wire pready; apb lul(pclk,presetn,pwrite,psel,penable,paddr,pwdata,prdata,pready);

reg[31:0] array[]; reg[31:0] memory_temp[1023:0]; reg[31:0] paddr_temp; reg[31:0] pwdata_temp; reg[31:0] prdata_temp; integer x, n = $urandom_range(5); initial begin $dumpfile("dump.vcd"); $dumpvars(); end initial begin pclk=0; forever #5 pclk = ~ pclk; end task idle(); presetn = 0; penable = 0; psel = 0; pclk = 0; pwrite = 0; pwdata = 0; paddr = 0; endtask task write(); for(x=0; x

initial begin paddr = 0; pwdata = 0; psel = 0; penable = 0; pwrite = 0; pclk=0; presetn=0; penable=0; end initial begin $dumpfile("dump.vcd"); $dumpvars; end

/// clk generator /// initial begin forever #5 pclk = ~pclk; end initial begin @(negedge pclk); pwdata = $urandom; paddr = $urandom_range(1023); psel = 1; pwrite = 1; presetn = 1; penable = 1; @(negedge pclk); pwrite = 0; penable =0; @(negedge pclk); penable = 1; #50 $finish; end endmodule */

Answer Correctly!!