Q$3)5-$stages processor has the following latencies:

Fetch

$300$ ps

Decode

$500$ ps

Execute

$350$ ps

Memory

$600$ ps

Write back

$100$ ps

Hint: latency$=$ execution time of $1$ instruction

$($a$)$ ilf the processor is a single cycle non$-$pipelined what is the cycle time for the processor? What is the

latency of an instruction for the processor?

$($b$)$ If the processor is pipelined what is the cycle time for the processor? What is the latency of an

instruction for the processor?

$($c$)$ If you could split one of the pipeline stages into $2$ equal halves, resulting into $6$ stages, which one would

you choose$(2)?$ What is the new cycle time$(3)?$ What is the new latency$(3)?$