Q$3.$ The basic single $-$cycle MIPS implementation in the above figure $($Fig$.1)$ can only implement some instructions. New instructions can be added to existing Instruction Set Architecture $($ISA$),$ but the decision whether or not to do that depends, among other things, on the cost of the complexity the proposed addition introduces into the processor datapath and control. Assume the following new instruction is added to our MIPS processor. Answer each of the following:

Instruction: LWI RT$,$ RD$($RS$)$

Interpretation: Reg $[$RT$]=$ Mem$[$Reg$[$RD$]+$ Reg$[$RS$]]$

Which existing blocks can be used for this instruction?

Which new functional blocks $($if any$)$ do we need for this instruction?

What new signals do we need $($if any$)$ from the control unit to support this instruction?

Q$4.$ Simplified and Implement a logic block that produces the following output.

$\backslash$table$[[$Inputs$,$Output$],[$A$,$B$,$C$,$D$,$E$],[0,0,0,0,1],[0,0,0,1,0],[0,0,1,0,0],[0,0,1,1,1],[0,1,0,0,1],[0,1,0,1,0],[0,1,1,0,0],[0,1,1,1,1],[1,0,0,0,1],[1,0,0,1,1],[1,0,1,0,0],[1,0,1,1,1],[1,1,0,0,1],[1,1,0,1,1],[1,1,1,0,1],[1,1,1,1,0]]$