Question: Question 2 ( 4 0 % ) - Consider a MIPS processor that uses the five - stage pipeline described in class ( IF ,

Question 2(40%)- Consider a MIPS processor that uses the five-stage pipeline described in class (IF, ID, EXE, MEM, WB). The processor is used to execute the following sequence of instructions:
SW $s0,80($s3) LW $s4,8($s0) ADDI $s5, $s4,10 AND $s6, $s4, $s4 ADD $s7, $s4, $s5
Pipelined execution: assume that the clock cycle is 2 ns.
A. Indicate the data dependences that result due to the execution of this instructions sequence. The data dependency occurs when an instruction produces a value in a given pipeline stage, and a subsequent instruction consumes that value in another pipeline stage.
B. Which hazard type occurs due to the data dependency described in A?

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