Question $2$: Given the data in Table $9-4$ shown below, to find the following

Draw a graph of input and output voltage specifications for the $4000B$ CMOS and the $74$ALSTTL IC series.

From your graphs of the two IC series, find the HIGH$-$ and LOW$-$level noise margins.

From your graphs, is there a problem in directly interfacing:

$($a$)$ The $4000B$ CMOS to the $74$ALSTTL? and why according to your answer?

$($b$)$ The $74$ALSTTL to $4000B$ CMOS? and why according to your answer?

How many $74$ALSTTL loads can be driven by a single $4000B$ CMOS gate?

Does the $74$TTL to $4000B$ CMOS interfacing require a pull up resistor? And why according to your answer?