Question marks, CLO$3]$

Assume the main memory accesses take $70$ ns and that $36\%$ of all instructions access data memory. The following

table shows data for $L1$ cache to two different processors $P1$ and $P2.$

a$)$ Assume that the $L1$ hit time determines the cycle times for $P1$ and $P2,$ what are their respective clock rates?

b$)$ What is the Average Memory Access time for P$1$ and P$2?$

c$)$ Assume the CPI of $1\mathrm{.}0$ without the memory stalls, what is the total CPI for P$1$ and P$2?$ Which processor

will be fast and why?