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4. A multi-cycle processor P1 executes load instructions in 15 cycles, store instructions in 12 cycles, arithmetic instructions in 6 cycles, and branch instructions in 6 cycles. Consider an application A where 25% of all instructions are load instructions, 20% of all instructions are store instructions, 40% of all instructions are arithmetic instructions, and 15% of all instructions are branch instructions. N new design of the processor doubles the clock frequency of Pl. However, the latencies of the load, store, arithmetic, and branch instructions increase by 2, 3, 2, and 1 cycles, respectively. We call this new processor P2. (a) What is the global CPI for each implementation? (b) Find the clock cycles required in both cases. (c) Find the time required on each processor if the compiler produce IE7 instructions to run the application. (d) If the P1 consumes IOOW of dynamic power and 30W of static power, It completes a program in 10 seconds. What is the consumption on processor Pl if voltage down by and frequency is 5GHz. 2