Question: Suppose that a computer has a processor with two L1 caches, one for instructions and one for data, and an L2 cache. Let be the

Suppose that a computer has a processor with two L1 caches, one for instructions and one for data, and an L2 cache. Let be the access time for the two L1 caches. The miss penalties are approximately 15 for transferring a block from L2 to L1, and 100 for transferring a block from the main memory to L2. For the purpose of this problem, assume that the hit rates are the same for instructions and data and that the hit rates in the L1 and L2 caches are 0.94 and 0.84, respectively. (a) What value for h1 would be needed to reduce tavg to 1.6 (assume h2 remains)? (b) Can the same result be achieved by improving the hit rate of L2 (assume h1 remains)?

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