The JK flip flop can be described by the table below. Using Verlog, not System Verilog, write a JK flipflop module with inputs J, K, clk, and outputs Q and Qn. Use a Boolean expression, which you can derive from the table if you dont remember it. Use the minimum number of lines, good organization and indentation.

J	K	Q	Q*
0	0	0	0
0	1	0	0
1	0	0	1
1	1	0	1
0	0	1	1
0	1	1	0
1	0	1	1
1	1	1	0

#1) Write a test bench that shows the operation of the JK flipflop is as described in the table. It should test each case, but not necessarily in the order of the table.