Question: The Moore ( or synchronous ) sequence detector circuit has the inputs X , Rx , CLK and the output Z as shown in Figure

The Moore (or synchronous) sequence detector circuit has the inputs X, Rx, CLK and the output Z as shown in Figure 1. Figure 1: Port description of sequence detector When the Rx signal goes from 0 to 1, the sequence detector is operational, and the input X is ready to receive a binary signal. When Rx =0, the circuit resets and the output Z is 0. The output Z goes to 1 when X receives the input sequence of X3X2X1X0, where X0 is the first bit of the sequence, followed by X1 at the next clock cycle and so on. The output Z will hold its value of 1 until X receives a second sequence of Y3Y2Y1Y0, to make the output Z go to 0. Once again, Y0 is the first bit of the sequence, followed by Y1 at the next clock cycle and so on. For all the other inputs of X the output Z will hold its value. The sequences X3X2X1X0 and Y3Y2Y1Y0 are determined by using the last three digits of your student number to form a decimal number ranging from 0 to 999. Converting this decimal number to binary yields a maximum of 10 bits (Z1Z0Y3Y2Y1Y0X3X2X1X0) where X0 is the least significant bit and Z1 is the most significant bit. Let the first four least significant bits be used for X3X2X1X0 and let the next four bits be used for Y3Y2Y1Y0. Bits Z1Z0 can be ignored. If any of the sequences for X3X2X1X0 and Y3Y2Y1Y0 are 0000 then change the sequence to 0001 and if any of the sequences are 1111 then then change the sequence to 0111.
show me the circuit diagram using flip flop, for the decimal number (070)

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