timescale Ins / Ips module mainfunction (input a,b,c, output y): assign y(ab) (alc) endmodule "timescale ins / Ipa module testbenchi reg a,b,c; mainfunction dt(.a(a)..b(b)..c(e),y(); initial begin 4-0 -0) 00:010 11 (4-1) sdisplay("y-logic 0") end endmodule Which of the following is true for the two verllog codes above? 1. Behavioral design level is used. II Outputly) is equal to logic 1 and the text yelogic O appears in the simulation ill. The combinational circuit designed in the code includes 3 logic gates IV. A net has to be added to the code for the output