To execute the following assembly code segment using a $5-$stage MIPS pipelined processor,

Instruction ID

Instruction

$1$

lw $t$0,0($$t$1)$

$2$

add $t$2,$ $t$0,$ $t$2$

$3$

addi $t$3,$ $t$2,8$

$4$

lw $s$0,0($$s$1)$

$5$

add $s$2,$ $s$0,$ $s$0$

$6$

addi $s$3,$ $s$2,9$

$7$

$...$

a$.$ How many different data hazards can you find? Where are they $($e$.$g$.$ between ins$\_1$ and ins$\_2)?$

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b$.$ Suppose the processor had NO $$forwarding$$ feature and the compiler could NOT reorder the instructions to avoid pipeline stalls, pipeline stall is the only approach to handle the data hazards. How many clock cycles it would take to execute the above code segment?

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c$.$ Suppose the processor had both the $$forwarding$$ feature and instruction reordering feature, how many clock cycles it would take to execute the above code segment?

Write down the reordered instructor order and mark which hazards could be solved by forwarding, which hazard could be solved by recordering.

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