use Vivado 16.4 Webpack to write and simulate a hex to seven segment display convert. I've tried doing it but I kept receiving errors, here is an outline of how it is supposed to look. Also, there needs to be a test bench file. The outline is below. Originally, I've written it using a switch case. I did not receive any errors for it, but the test bench file does not seem to work. Thanks, for the help.

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity encoder is Port ( -- Enter your port definitions here ); end encoder;

architecture Behavioral of encoder is

-- temporary signal to make our assignment of values (a through g) simpler signal seven_seg : std_logic_vector(6 downto 0);

begin seven_seg <= -- Enter your code to assign values for the entire 7 bits (a through g) based on the hex input -- Extract each individual bit and assign it to the 7 outputs a <= seven_seg(6); b <= seven_seg(5); c <= seven_seg(4); d <= seven_seg(3); e <= seven_seg(2); f <= seven_seg(1); g <= seven_seg(0);

end Behavioral;

Test bench file

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library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity encoder_tb is -- Port ( ); end encoder_tb;

architecture Behavioral of encoder_tb is

component encoder Port ( hex_in : in STD_LOGIC_VECTOR(3 DOWNTO 0); a : out STD_LOGIC; b : out STD_LOGIC; c : out STD_LOGIC; d : out STD_LOGIC; e : out STD_LOGIC; f : out STD_LOGIC; g : out STD_LOGIC ); end component; signal counter : unsigned(3 downto 0):="0000"; signal hex_in : std_logic_vector(3 downto 0); signal a, b, c, d : std_logic; signal e, f, g : std_logic; begin uut: encoder port map( hex_in => hex_in, a => a, b => b, c => c, d => d, e => e, f => f, g => g ); hex <= std_logic_vector(counter); --increments the counter using a process --use a 20ns delay between each combination --Enter your code here