Question: VERILOG STOPWATCH PROGRAM: This is a verilog program that is essentially a state machine I also need to clock it so that the default 50MHz

VERILOG STOPWATCH PROGRAM:

This is a verilog program that is essentially a state machine

I also need to clock it so that the default 50MHz clock counts as a second.

There are 3 states that are specified, but more can be added:

Reset: resets all states

start: The countdown starts from 3 to 2 to 1 in a hex display and then begins countdown from 0.000 to 14.999 if 14.999 is reached, will enter a END state that will stay until reset is pressed.

The start and finish are assigned to a single input (A) the input will go to the start state if it is at the reset state.

finish: displays the value of the timer (00.000 to 14.999) for a second and then resume counting if its not 14.999 already. For example, if A is pressed at 10.150, it will stay for 1 second, and after that second, the timer will keep counting during the pause and start from 11.150. We can do this display up to 3 times. if A is detected during the start/finish state, it will be in the finish state.

The countdown should be displayed on a HEX display, for example HEX4-HEX0.

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