VERLOG CODE: Project.v -------------------------------------------------------------

Verlog code: Project.v --------------------------------------------------------------------------------------------------------------------

//32-bit adder //To get all scores, you cannot use arithmetic operators in this module. module adder(input [31:0] x, input [31:0] y, input ci, output reg co, output reg [31:0] s); //write your code here endmodule

//32-bit shifter //To get all scores, you cannot use shift operators in this module. module shifter(input [31:0] x, input [4:0] c, input [1:0] op, output reg [31:0] y); //write your code here endmodule

//32-bit ALU //To get all scores, you cannot use arithmetic operators in this module. module ALU( input [31:0] a, input [31:0] b, input [2:0] op, output reg [31:0] s); //write your code here endmodule

Adder nt a 32-bit adder. Input: x (32 bits), y (32 bits), ci (1 bit) Output: co (1 bit), and s (32 bits). This adder should calculate the result of x y ci, and send the result to s and also the carry to co. For example, if x = 0:00000001, y = 0xFFFFFFFF, and co = 1, then the output should be s = 0x00000001 and ci 1. Notice that you cannont use arithmetic operators (including +, -, *, /, *+, %) in Verilog in this module Shifter Implement a 32-bit shifter Input: x (32 bits), c (5 bits), and op (2 bits). Output: y