Vivado 2018.2

design a seven segment display using the always_comb block in Vivado

design a 2:1 multiplexor of Varibale length (using the parameter keyword) in Vivado

Create a Top Level Design that should have 4-bit input A, 4-bit input B, 7-bit output seg, and 4-bit output an. Create your top level file to connect the sum output of the RCA to the seven segment and Co output of the RCA to the selector of the mux.

Test on Basys Board III

I need help with all of this as well as the constraints file for the basys board. Mostly the top file and constraints though.

I have this so far

Half-Adder

Full-Adder

Ripple Carry Adder

10 module HA( 12 13 14 input A, input B, output Co, output S 16 17 ssign S(A B) assign Co(A & B) 2 19 20endmodule 10 module HA( 12 13 14 input A, input B, output Co, output S 16 17 ssign S(A B) assign Co(A & B) 2 19 20endmodule