What is the baseline performance $($in cycles, per loop iteration$)$ of the code sequence in Figure$-1$

if no new instruction$$s execution could be initiated until the previous instruction$$s execution had

completed? Ignore front$-$end fetch and decode. Assume that execution does not stall for lack

of the next instruction, but only one instruction$/$cycle can be issued. Assume the branch is taken,

and that there is a one$-$cycle branch delay slot. $($In the following code, you may assume Rx is as

x$1$ register, Ry register is as x$2$ register$)$b$-)$ Considering true data dependencies and functional unit latencies, reorder$($schedule$)$ the

instructions to improve performance of the code in Figure$-1.$ Calculate the required cycles per

iteration of the loop.

c$-)$ Using different registers to prevent name dependencies, hand$-$unroll two iterations of the loop in

your reordered code obtained from $($b$).$ Calculate the required cycles per iteration of the loop.

d$-)$ Now, reorder$($schedule$)$ the unrolled code obtained from $($c$).$ Calculate the required cycles per

iteration of the loop.