Question: Why I could not run the simulation with my code. Please help me to fix it. This is my design sources: This is my testbench:

Why I could not run the simulation with my code. Please help me to fix it.

This is my design sources:

Why I could not run the simulation with my code. Please help

This is my testbench:

me to fix it. This is my design sources: This is my

This is errors:

testbench: This is errors: General Messages (4 errors) [Vivado 12-4473] Detected error

General Messages (4 errors) [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. > [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Ha Tran/EE178 Labs/Lab2/Lab2.sim/sim_1/behav/xsim/elaborate.log' file for more information. (1 more like this) (1) [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. Simulation (2 errors) sim_1 (2 errors) (1) [VRFC 10-2063] Module not found while processing module instance [full_adder_join.v:27] [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed

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