working on vivado, tasked to write a testbench for my $2-1$ MUX but the compiler keeps saying my syntax is bad on line $6$ by 'reg'. what am i missing?

$//2-1$mux code

$`$timescale $1$s $/1$s

module Mux$\_2$x$1($Y$,$ I$0,$ I$1,$ S$)$;

input I$0,$I$1,$S;

output Y;

wire sb$,$ a$,$ b;

not$($sb$,$S$)$;

and$($a$,$sb$,$I$0)$;

and$($b$,$S$,$I$1)$;

or$($Y$,$a$,$b$)$;

endmodule

$//$mux$\_$tb code

$`$timescale $1$ns $/1$ps

module Mux$\_2$x$1\_$tb

reg I$0,$ I$1,$ S;

wire Y;

Mux$\_2$x$1$ uut$($I$0,$ I$1,$ S$,$ Y$)$;

initial begin

S $=0$; I$0=0$; I$1=1$;

#$10$

S $=0$; I$0=1$; I$1=0$;

#$10$

S $=1$; I$0=1$; I$1=0$;

#$10$

S $=1$; I$0=0$; I$1=1$;

#$10$

$finish$()$;

end

endmodule