Question: Write a Verilog test bench file for the module in Question 3 using the following test patterns: - Initially, apply AB=10 - After 5 time

Write a Verilog test bench file for the module in Question

Write a Verilog test bench file for the module in Question 3 using the following test patterns: - Initially, apply AB=10 - After 5 time units (counting from initial time), apply AB=00 - After 14 time units (counting from initial time), apply AB=10 - After 21 time units (counting from initial time), apply AB=11 - Stop simulation at time = 30 time units. Use the box below to type your Verilog test bench module

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