Question: Write a Verilog test bench file for the module in Question 1 using the following test patterns: - Initially, apply AB=00 - After 7 time

Write a Verilog test bench file for the module in Question

Write a Verilog test bench file for the module in Question 1 using the following test patterns: - Initially, apply AB=00 - After 7 time units (counting from initial time), apply AB=01 - After 14 time units (counting from initial time), apply AB=11 - Stop simulation at time =25 time units

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