Write code in SystemVerilog for Vivado to test this OTTER register file. I have this so far:

module REGFILE$($

input $[4$:$0]$ ADR$1,$

input $[4$:$0]$ ADR$2,$

input $[4$:$0]$ WADR,

input $[31$:$0]$ WDATA,

input $[0$:$0]$ WE$,$

output $[31$:$0]$ RS$1,$

output $[31$:$0]$ RS$2$

$)$;Figure $3\mathrm{.}1$: Register File Black Box Diagram