Write the SystemVerilog code for this OTTER register file module. I have this so far:

module REGFILE$($

input $[4$:$0]$ ADR$1,$

input $[4$:$0]$ ADR$2,$

input $[4$:$0]$ WADR,

input $[31$:$0]$ WDATA,

input $[0$:$0]$ WE$,$

input clk$,$

output $[31$:$0]$ RS$1,$

output $[31$:$0]$ RS$2$

$)$;

reg $[31$:$0]$ REGFILE $[31$:$0]$;

always @$($posedge clk$)$ begin

if $($WE$)$ begin

REGFILE$[$WADR$]<=$ WDATA;

end

end

assign RS$1=$ REGFILE$[$ADR$1]$;

assign RS$2=$ REGFILE$[$ADR$2]$;

I also have to initialize all registers to zero and this code was given to help with that:

logic $[15$:$0]$ ram $[0$:$511]$;

$//$ Initialize the memory to be all $0$s

initial begin

int i;

for $($i$=0$; i$<512$; i$=$i$+1)$ begin

ram$[$i$]=0$;

end

end

I$\text{'}$m not sure how to implement the initializing to $0$ part.