Write test bench code in SystemVerilog for Vivado to test this OTTER register module. I have this for my code for the register.

module REGFILE$($

input $[4$:$0]$ ADR$1,$

input $[4$:$0]$ ADR$2,$

input $[4$:$0]$ WADR,

input $[31$:$0]$ WDATA,

input $[0$:$0]$ WE$,$

input clk$,$

output $[31$:$0]$ RS$1,$

output $[31$:$0]$ RS$2$

$)$;

reg $[31$:$0]$ REGFILE $[31$:$0]$;

always @$($posedge clk$)$ begin

if $($WE$)$ begin

REGFILE$[$WADR WDATA;

end

end

assign RS$1=$ REGFILE$[$ADR$1]$;

assign RS$2=$ REGFILE$[$ADR$2]$;

endmoduleFigure $3\mathrm{.}1$: Register File Black Box Diagram