Question: Write code in Verilog with a test bench Implement the IBM RS/6000 FP Multiply-Add-Fused (MAF) Functional Unit shown below 2 stage pipelined MAF [multiply- add-fused]

Write code in Verilog with a test bench

Implement the IBM RS/6000 FP Multiply-Add-Fused (MAF) Functional Unit shown below 2 stage pipelined MAF [multiply- add-fused] unit Takes 3 inputs A, B, and C Performs (A x B)C FP multiply instruction is executed as (A x B)+0 FP add performed by MAF as AB (Ax l)+C (A B) + C Round/Normalize Implement the IBM RS/6000 FP Multiply-Add-Fused (MAF) Functional Unit shown below 2 stage pipelined MAF [multiply- add-fused] unit Takes 3 inputs A, B, and C Performs (A x B)C FP multiply instruction is executed as (A x B)+0 FP add performed by MAF as AB (Ax l)+C (A B) + C Round/Normalize

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