Write the HDL gate level (structural) hierarchical description for 4-bit binary adder-subtractor. [IO specifications] You have 4-bit inputs A and B (signed radix), and 1-bit input M as control bit. You need to output 4-bit S as results, 1-bit C for carry (or borrow) out, 1-bit V for overflow. When M is 0, S is result of A plus B; when M is 1, S is the result of A minus B. Overflow bit V indicates whether 4 bit signed radix is enough to represent the correct answer S. V=1 means 4-bit signed radix has not enough bits, so we need more bits to present S. V=0 means 4-bits is enough, our output is correct in four bit signed radix. Step 1: design a 1-bit half_adder circuits and write it in structural code. Step 2: design a 1-bit full_adder by instantiating the half_adder. Step 3: make a 4-bit adder by instantiating the 1-bit full_adder. Step 4: make a 4-bit adder-subtractor following the figure below (taken from page 142 of the Mano, Ciletti textbook). Note here vector B will need to have a controlled complementor proceeding its input to the adder bits. (xor primitive)

Step 1: design a 1-bit half_adder circuits and write it in structural code.

Step 2: design a 1-bit full_adder by instantiating the half_adder.

Step 3: make a 4-bit adder by instantiating the 1-bit full_adder.

Step 4: make a 4-bit adder-subtractor following the figure below. Note here vector B will need to have a controlled complementor proceeding its input to the adder bits. (xor primitive).

Bs As B A2 B1 A Bo Ao 4-bit adder C4 C3 FA So Bs As B A2 B1 A Bo Ao 4-bit adder C4 C3 FA So