Write the Verilog HDL code for a 16-bit Universal Shift Register (negative-edge Subscript ed) at the behavioral-level of abstraction. The design should have control inputs enable and op. If enable is false, the universal shift register is disabled, and the universal shift register keeps its data. Else if op is equal to 0, the data in the universal shift register is reset to all zeroes. Else if op is equal 1, the data in the universal shift register is shifted to the left by 4 bits. Else if op is equal 2, the data in the universal shift register is shifted to the right by 4 bits. Else if op is equal 3, the data at the parallel input ports is loaded into the universal shift register