Question: Write the VHDL code for the following block diagram: entity problem X is port (a: in bit_vector (0 to 7 ); d: out bit_vector (0

Write the VHDL code for the following block diagram: entity problem X is port (a: in bit_vector (0 to 7 ); d: out bit_vector (0 to 2); end problem X; architecture structure of problem X is component B1 is generic (m, n: integer); port (x: in bit.vector (0 to m-1); y: out bit_vector (0 to n-1)); end component; component B2 is generic (m, n: integer); port (x: in bit_vector (0 to m-1); y: out bit_vector (0 to n-1)); end component

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